A. Field of the Invention
The present invention relates to a power semiconductor device such as a MOSFET, and in particular, to a semiconductor device and a method of manufacturing the semiconductor device that has a drift layer with a superjunction structure, or a parallel pn column structure or parallel pn layer structure. The superjunction structure comprises an n type column and a p type column alternately adjoining each other and extending in a vertical direction with respect to a principal surface of a semiconductor substrate.
B. Description of the Related Art
Semiconductor devices are generally classified into lateral devices having electrodes formed on one surface of a semiconductor substrate and vertical devices having electrodes formed on both surfaces of a semiconductor substrate. In a vertical semiconductor device, drift current in an ON state flows in a direction that is same as the direction for a depletion layer to extend in an OFF state caused by a reverse bias voltage. In a usual planar type n channel vertical MOSFET, the drift current flows vertically through a high resistivity n− drift layer in an ON state. Thus, if the current path in the n− drift layer is shortened, the drift resistance decreases and a substantial ON resistance of the MOSFET also decreases.
The n− drift layer with a high resistance becomes depleted in an OFF state and enhances a withstand voltage. Consequently, a thin n− drift layer narrows an expansion width of the depletion layer between the drain and base extending from the pn junction between the p base region and the n− drift layer, resulting in a lowered withstand voltage. Conversely, a semiconductor device exhibiting a high withstand voltage with a thick n− drift layer has a large ON resistance and increases a conduction loss. Thus, the ON resistance and the withstand voltage are in a trade-off relationship. This trade-off relationship is known to hold similarly with semiconductor devices such as IGBTs, bipolar transistors and diodes.
In order to cope with the problem of this trade-off relationship, a semiconductor device is known having a drift layer thereof with a superjunction structure composed of a parallel pn layer that is formed by joining alternately a p type semiconductor layer and an n type semiconductor layer containing high concentration of impurities.
FIG. 16 is a sectional view of an essential part of a conventional superjunction semiconductor device 500. The semiconductor device of FIG. 16 is a SJ-MOSFET having a superjunction (SJ) structure. The SJ-MOSFET has parallel pn layer 120 disposed on n type semiconductor substrate 101 (n+ drain region), parallel pn layer 120 being composed of n type semiconductor layer 210 and p type semiconductor layer 209. On parallel pn layer 120, device surface structure 104 is provided. Device surface structure 104 comprises p base region 103, and p+ contact region 105 and n+ source region 106 disposed in the surface region of p base region 103. Device surface structure 104 further comprises gate insulation film 107 disposed on a part of p base region 103 between n+ source region 106 and n type semiconductor layer 210 of parallel pn layer 120, gate electrode 108 disposed on gate insulation film 107, interlayer dielectric film 109 covering gate electrode 108, and source electrode 110 electrically connected with p+ contact region 105 and n+ source region 106. On the back surface of n type semiconductor substrate 101 provided is drain electrode 112. Parallel pn layer 120 is composed of p type semiconductor layer 209 and n type semiconductor layer 210 arranged alternately in contact with each other.
In superjunction semiconductor device 500 having parallel pn layer 120 containing a high concentration of impurities, a depletion layer in an OFF state extends laterally from each pn junction which lies in a vertical direction of parallel pn layer 120 to make the whole drift layer depleted, resulting in a high withstand voltage. The drift layer of n type semiconductor layer 210 is allowed to be high concentration, achieving low ON resistance.
FIGS. 17 through 19 are sectional views of an essential part of the superjunction semiconductor device of FIG. 16 showing a manufacturing method of the device following the sequence of steps of the manufacturing procedure.
(1) First, as shown in FIG. 17, high resistivity n type semiconductor layer 201 is epitaxially grown on n type semiconductor substrate 101. Then patterning and ion implantation are conducted on n type semiconductor layer 201 of an epitaxial layer to form p type ion implantation layer 207 and n type ion implantation layer 208.
(2) Then, as shown in FIG. 18, by repeating the step (1), several layers of semiconductor layers 201 through 205 each including p type ion implantation layer 207 and n type ion implantation layer 208 are laminated. A semiconductor layer 206 is formed on the semiconductor layer 205.
(3) Then, as shown in FIG. 19, driving heat treatment is conducted for diffusion of the impurities in p type ion implantation layer 207 and in n type ion implantation layer 208. As a result, the p type ion implantation layers in the semiconductor layers are joined vertically to form p type semiconductor layer 209 and the n type implantation layers in the semiconductor layers are joined vertically to form n type semiconductor layer 210. P type semiconductor layer 209 and n type semiconductor layer 210 compose parallel pn layer 120 with a superjunction structure. This procedure is a method for forming parallel pn layer 120 called a multi-stage epitaxial growth method.
On parallel pn layer 120 with a superjunction structure, the following are formed: p base region 103, p+ contact region 105, n+ source region 106, gate insulation film 107, gate electrode 108, interlayer dielectric film 109, and source electrode 110. On the back surface of the n type semiconductor substrate, under parallel pn layer 120, drain electrode 112 is formed. Thus, superjunction semiconductor device 500 is completed. The above-mentioned regions of a device surface structure occasionally are formed on an n type layer that is additionally formed on parallel pn layer 120.
Parallel pn layer 120 having a superjunction structure can be formed by a trench embedding method as well as by the multi-stage epitaxial growth method described above. In the trench embedding method, though not depicted, an epitaxial layer is formed on a semiconductor substrate, and a trench is formed in the epitaxial layer. In this trench, a semiconductor layer of a conductivity type opposite to that of the epitaxial layer is embedded.
Descriptions of the following documents are provided:
Patent Document 1
    Japanese Unexamined Patent Application Publication No. 2001-119022Patent Document 2    U.S. Pat. No. 5,216,275Patent Document 3    International Patent Application Publication WO2011/093473Patent Document 4    Japanese Unexamined Patent Application Publication No. 2010-225831Patent Document 5    Japanese Unexamined Patent Application Publication No. 2007-235080.
Patent Document 1 discloses a multi-stage epitaxial growth method in which epitaxial growth and ion implantation are repeated to form a parallel pn layer having a superjunction structure, similar to the one described above.
Patent Document 2 discloses a trench embedding method for forming a parallel pn layer with a superjunction structure, in which an n type semiconductor layer is epitaxially grown on an n+ type semiconductor substrate and a trench is dug in the n type layer. A p type semiconductor layer is epitaxially grown in the trench.
Patent Document 3 discloses achieving improvement of the trade-off relationship between Eoff and turning OFF dV/dt in superjunction semiconductor devices, which are SJ-MOSFETs in the examples of the document, fabricated by a multi-stage epitaxial growth method and a trench embedding method. The Eoff is a turning OFF loss generated in a turning OFF process of the MOSFET. The turning OFF dV/dt is a rising up rate of a re-applied voltage to which the MOSFET is subjected in the turning OFF process of the MOSFET. The disclosure in Patent Document 3 is further described in the following.
In the superjunction semiconductor device manufactured by a multi-stage epitaxial growth method, the impurity concentration in the upper portion of an n type semiconductor layer, i.e., an n type column, composing a parallel pn layer is 1.5 to 2.0 times higher than that in the lower portion of the n type column, to make a depletion layer hardly extend in turning OFF operation. Thus, the trade-off relationship between the Eoff and the turning OFF dV/dt is improved.
In the superjunction semiconductor device manufactured by a trench embedding method, on the other hand, the impurity concentration of a p type semiconductor layer, i.e., a p type column, is enhanced in a portion from the top surface to a position in a range of 1/1.5 to ⅓ of the trench depth. The impurity concentration in the surface region of an n type column of an epitaxial layer is made 1.2 to 3.0 times higher than that in the lower portion of the n type column. The p type columns and the n type columns compose a parallel pn layer having a superjunction structure by the trench embedding method. Thus formed parallel pn layer having a superjunction structure improves the trade-off relationship between the Eoff and the turning OFF dV/dt.
Patent Document 4 discloses a method of forming a parallel pn layer having a superjunction structure by a trench embedding method employing a trench with an aspect ratio at lease 8. The disclosure of Patent Document 4 is described in more detail in the following.
In the method disclosed in Patent Document 4, a trench with a taper at the top thereof is formed in the first conductivity type semiconductor substrate and, on the taper, first conductivity type impurities are ion-implanted. After that, the trench is filled with an epitaxial layer of the second conductivity type. Thus, a parallel pn layer is formed. On the surface of the parallel pn layer, a semiconductor layer of the second conductivity type is formed. In the surface region of this semiconductor layer, an emitter layer, or a source layer, is formed on which a gate electrode is formed.
The tapered configuration allows plenty of impurities to be injection by oblique implantation to this place, and compensates for the amount of impurities decreased due to removed volume by forming the taper. Consequently, charge balance in the tapered portion of the parallel pn layer is held thereby avoiding drop of a withstand voltage.
Patent Document 5 discloses that the impurity concentration in an n type semiconductor layer, i.e. an n type column, is adjusted by two or more times of ion implantation with varied tilting angles into a side wall of a trench.
FIG. 20 shows schematically the relationship between the Eoff and the turning OFF dV/dt. Improvement of the trade-off relationship is represented by transfer of the curve Z in the direction of the arrow toward smaller values of the Eoff and the turning OFF dV/dt.
However, in order to manufacture a superjunction semiconductor device 500, as shown in FIG. 16 and disclosed in Patent Document 3, by means of multi-stage epitaxial growth, five or six steps need to be repeated including a step of epitaxial growth, a step of ion implantation for n type impurity ion implantation, a step of photolithography, and a step of ion implantation for p type impurity ion implantation. This procedure needs multiple steps and high cost.
The trench embedding method disclosed in Patent Document 3 forms a high concentration n type epitaxial layer on a low concentration n type epitaxial layer before forming a trench. Because the epitaxial growth method is employed for forming the high concentration n type semiconductor layer, the method of Patent Document 3 is costly.
In the method of Patent Document 4, the high concentration n type semiconductor layer is formed in order to obtain charge balance in the tapered part. Because a p base layer is formed on this tapered part, the impurity concentration in the n type column under the p base layer is homogeneous, and thus, the effect for improving the trade-off relationship between the Eoff and the turning OFF dV/dt is little.
None of Patent Documents 1 through 5 discloses or suggests making an upper portion of the n type semiconductor layer i.e., n type column, composing the parallel pn layer to be high impurity concentration by means of ion implantation in the process of forming the parallel pn layer having a superjunction structure in the trench embedding method. In addition, none of Patent Documents 1 through 5 discloses or suggests that the trade-off relationship between the Eoff and the turning OFF dV/dt is improved by forming a high concentration n type semiconductor layer in the upper portion of an n type semiconductor layer, i.e., n type column, employing an ion implantation process.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.